This application claims the priority benefit of Taiwan application serial no. 89101682, filed Feb. 1, 2000.
1. Field of the Invention
The present invention relates to the method of improving the latch-up effect in complementary metal-oxide semiconductor (CMOS) process. More particular, the present invention relates to a fabrication method and a structure performed ion implantation on the cathode or the anode of parasitic latch-up silicon-controlled rectifiers (SCR). Therefore, the impedance in the parasitic SCR conducting path can be raised to increase the trigger level, so as to prevent the occurrence of latch-up effect induced by noise.
2. Description of the Related Art
In the CMOS circuit design, to avoid the body effect, the bulk of a P-channel MOS (PMOS) is typically connected to the most positive voltage, and the bulk of an N-channel MOS (NMOS) is connected to the most negative voltage. Thus, a parasitic SCR device is formed. The most positive voltage is applied to the anode of the SCR device, while the most negative voltage is applied to the cathode of the SCR device. When the distance between the PMOS and the NMOS is small enough, the parasitic SCR device is easily triggered on to induce the latch-up phenomenon. Under normal operation, this latch-up path is not conducted. However, while noise exists as a trigger, the parasitic SCR device is easily conducted to cause a regeneration which results in a large current flowing through the IC and momentary or permanent loss of IC function.
The latch-up effect has been disclosed in some publication such as the issued US patents as follows:
1. The U.S. Pat. No. 5,879,967, xe2x80x9cMethods forming power semiconductor devices having latch-up inhibiting regionsxe2x80x9d by Tae-Hoon Kim et al. in Mar. 19, 1999.
2. The U.S. Pat. No. 5,861,330, xe2x80x9cMethod and Structure to reduce latch-up using edge implantsxe2x80x9d by Faye D. Baker et al. in Jan 19, 1999.
3. The U.S. Pat. No. 5,831,313, xe2x80x9cStructure for improving latch-up immunity and interwell isolation in a semiconductor devicexe2x80x9d by Chung-Chyung Han et al. in Nov. 3, 1998.
4. The U.S. Pat. No. 5,821,589, xe2x80x9cMethod for CMOS latch-up improvement by mev billi (buried implanted layer for lateral isolation) plus buried layer implantationxe2x80x9d by John O Borland et al. in Oct. 13, 1998.
5. The U.S. Pat. No. 5,770,504, xe2x80x9cMethod for increasing latch-up immunity in CMOS devicesxe2x80x9d by Jeffery S. Brown et al. in Jun. 23, 1998.
FIG. 1 is a cross-sectional view of a conventional parasitic SCR device parasitic in a CMOS process. The SCR device is equivalent to a two-terminal circuit comprising two bipolar junction transistors (BJT) including the lateral npn BJT 12 and the vertical pnp BJT 14, two resistors including the substrate resistor Rsub 16 and the n-well resistor Rwell 18.
FIG. 2 shows the equivalent circuit schematic diagram of the SCR device. Under certain conditions such as terminal over voltage stress, transient displacement currents of ionizing radiation, lateral currents in the well and substrate can cause sufficient Ohmic drop due to the well resistance Rwell 18 and the substrate resistance Rsub 16, hence forward biasing emitter-base junctions and activating both bipolar devices, the npn BJT 12 and the pnp BJT 14. When the current gain product of the two BJTs is sufficient to cause regeneration, the pnpn SCR can be switched to a low impedance, high current state. This condition is defined as latch-up. To eliminate or reduce latch-up possibility, the holding voltage at the xe2x80x9cONxe2x80x9d state of the SCR device has to be maintained at higher voltage then VDD, or the current gain product of the npn BJT 12 and the pnp BJT 14 has to be kept at less than 1, or the emitter-base junctions of both BJT have to be kept at non-forward bias situation.
Numerous methods have been proposed to eliminate or reduce latch-up possibility, which comprises:
1. Using an epitaxial wafer.
2. Forming a retrograde well.
3. Forming a shallow trench isolation.
4. Using the silicon on insulator (SOI) technique.
5. Forming guard rings.
FIG. 3 shows a conventional method using epitaxial wafer to prevent the latch-up effect. To decouple the two BJTs shown in FIG. 2, one can dramatically reduce the resistance Rwell 18 or Rsub 16. Rwell 18 can be reduced by increasing the well doped concentration, but a too heavily doped well can result in the MOSFET performance in the well being affected. Alternatively, the Rsub 16 can be reduced by using an expitaxial layer on a heavily doped substrate as shown in FIG. 3. Because the heavily-doped substrate is farther away from the active channel region, this method does not affect the MOSFET performance.
In FIG. 4, a prior art to prevent latch-up by forming guard rings is shown. The path 30 indicates the latch-up current path. The PMOS and NMOS are guarded by the guard rings 32, 34, respectively. Because the latch-up current path has been broken by the guard ring 32 and 34, the noise current injected into the well and substrate will be absorbed by the guard rings 32 and 34, respectively. Thus, the latch-up immunity of the CMOS device structure can be dramatically increased.
The present invention is directed to provide a structure using latch-up implantation to improve the latch-up immunity in CMOS IC""s. The structure comprises a first conductive type substrate, a second conductive type well, a first and a second transistors, a lightly doped first conductive type region, a lightly doped second conductive type region, a heavily doped first conductive type region and a heavily doped second conductive type region. The first transistor comprising a first source region, a first drain region and a first gate is formed on the second conductive type well. The first source region and the first drain region comprise heavily dope of first conductive type. The second transistor comprising a second source region, a second drain region and a second gate is formed on the first conductive type substrate. The second source region and the second drain region comprise heavily dope of second conductive type. The lightly doped first conductive type region is located at a junction between the bottom of the first source region and the second conductive type well region, while the lightly doped second conductive type region is located between the bottom of the second source region and the first conductive type substrate. The heavily doped first conductive type region located in the first conductive type substrate is near the second source region, and the heavily doped second conductive type region located in the second conductive type well is near the first source region.
The invention further provides a method using latch-up implantation for improving the latch-up immunity in the CMOS process. A second conductive type well is first formed in a first conductive type substrate. A first and second polysilicon gates are formed above the second conductive type well and the first conductive type substrate, respectively. A first conductive type ion implantation is performed to form the heavily doped first conductive type source region and drain region in the second conductive type well, and a heavily doped first conductive type region in the first conductive type substrate. A second conductive type ion implantation is performed to form the heavily doped second conductive type source region and drain region in the first conductive type substrate, and the heavily doped second conductive type region in the second conductive type well. Following, a latch-up implantation is used to form a lightly doped first conductive type region which locates between the bottom of the heavily doped first conductive type source region and the bottom of the second conductive type well. Then the latch-up implantation is further used to form a lightly doped second conductive type region which locates between the bottom of the heavily doped second source region and the bottom of the first conductive type substrate. The orders of performing the first conductive type ion implantation and the second conductive type implantation can be interchanged. In addition, the sequence for performing the first and second conductive type latch-up implantation can also be reversed.
In the structure and the fabrication method mentioned above, using ion implantation to form lightly doped regions at the cathode and the anode of a parasitic SCR device where the latch-up effect is likely to occur, the impedance of the SCR conducting path is increased. Therefore, the immunity to the noise which can induce latch-up phenomenon is increased. The latch-up effect is thus prevented from occurring. Furthermore, the ion implantation process does not require additional layout area of IC""s, therefore, the flexibility of the circuit design is greatly enhanced.